This invention relates to a display control apparatus wherein a picture signal for a character, a pattern or the like and a luminance signal for endowing the picture signal with a luminance are synchronously derived, and wherein the logic between the picture signal and the luminance signal is taken so as to control the luminance of the picture signal.
A prior-art display control apparatus of this type will be described with reference to FIGS. 6 thru 9.
FIG. 6 is a block diagram of the prior-art display control apparatus. In the figure, numeral 1 designates a picture signal generator which produces a picture signal, numeral 2 a luminance signal generator which produces a luminance signal, numeral 3 a sync signal generator which produces a sync signal for synchronizing the picture signal produced from the picture signal generator 1 and the luminance signal produced from the luminance signal generator 2, numeral 4 a data latch circuit which latches and then delivers the picture signal produced from the picture signal generator 1 and the luminance signal produced from the luminance signal generator 2 in order to synchronize these signals, numeral 5 the picture signal line of the data latch circuit 4 which delivers the synchronized picture signal, and numeral 6 the luminance signal line of the data latch circuit 4 which delivers the synchronized luminance signal.
FIG. 7 is a detailed block diagram of the picture signal generator 1 in FIG. 6. In the figure, numeral 17 indicates a memory which stores pictures therein, numeral 18 an address generator which produces an address for deriving the picture stored in the memory 17, and numeral 19 a parallel-to-serial converter which converts the parallel signals of the picture derived from the memory 17 on the basis of the output of the address generator 18, into serial signals and delivers them as a picture signal.
FIG. 8 is a detailed block diagram of the luminance signal generator 2 in FIG. 6. In the figure, numeral 22 indicates a memory which stores luminances therein, numeral 23 an address generator which produces an address for deriving the luminance stored in the memory 22, and numeral 24 a parallel-to-serial converter which converts the parallel signals of the luminance derived from the memory 22 on the basis of the output of the address generator 23, into serial signals and delivers them as a luminance signal.
FIG. 9 is a detailed block diagram of the sync signal generator 3 in FIG. 6. In the figure, numerals 27 indicate CMOS-type inverters which are connected in series into three stages, numerals 29 and 30 indicate first and second resistors which are connected in series between the input end of the first-stage inverter 27 and the output end of the third-stage inverter 27, respectively, and numeral 28 indicates a capacitor which is interposed between the node of the second-stage and third-stage inverters 27 and the node of the first and second resistors 29, 30.
Next, the operation of the prior-art display control apparatus thus constructed will be described.
In the picture signal generator 1, the memory 17 storing pictures therein is accessed using an address delivered from the address generator 18, so as to derive a picture composed of parallel signals. The derived picture composed of the parallel signals is converted by the parallel-to-serial converter 19 into a picture composed of serial signals, which is delivered to the data latch circuit 4 as a picture signal composed of time series pulses.
In this case, the operations of the address generator 18 and the parallel-to-serial converter 19 are performed in synchronism with pulses provided from the sync signal generator 3. Likewise, in the luminance signal generator 2, the memory 22 storing luminances therein is accessed using an address delivered from the address generator 23, so as to derive the luminance composed of parallel signals.
The derived luminance composed of the parallel signals is converted by the parallel-to-serial converter 24 into a luminance composed of serial signals, which is delivered to the data latch circuit 4 as a luminance signal.
Meanwhile, in the sync signal generator 3, an oscillator circuit is constructed of the series circuit of the inverters 27 connected in the three stages, the first and second resistors 29, 30 and the capacitor 28, whereby pulses at a predetermined frequency are delivered to the data latch circuit 4.
Here, on the basis of the pulses of the predetermined frequency produced from the sync signal generator 3, the data latch circuit 4 synchronizes the picture signal delivered from the picture signal generator 1 and the luminance signal delivered from the luminance signal generator 2 and provides the synchronized picture signal and luminance signal through the picture signal line 5 and luminance signal line 6, respectively.
Next, the relationship between the picture signal and the luminance signal will be described with reference to FIG. 10.
FIG. 10 is a diagram of the waveforms of the picture signal, luminance signal and sync signal. As illustrated in the figure, when one cycle of the sync signal is assumed to be a fundamental period, the pulse widths of the true and false levels of both the picture signal and the luminance signal are integral times the fundamental period, and also the phases of both the signals are in agreement.
FIG. 11 is a diagram in which the waveforms in one cycle of the sync signal in FIG. 10 are enlarged. As seen from the figure, the rises and falls of the pulses of the picture signal and the luminance signal require certain time intervals, which cannot become zero, so that the waveforms are distorted without becoming perfect square waves.
Now, another example of a prior-art display control apparatus will be described with reference to FIG. 12.
FIG. 12 has a block diagram showing the arrangement of the prior-art display control apparatus. In the figure, numerals 7 and 8 denote low-pass filters which are respectively disposed midway of the picture signal line 5 and luminance signal line 6 and each of which is construct ed of a coil and a capacitor.
In recent years, the prevention of EMI (electromagnetic interference) has been requested. In this example of arrangement, therefore, the low-pass filters 7 and 8 are disposed so that radio frequencies may not be transmitted to, for example, an external interface portion.
In this case, the rise T.sub.r and fall time T.sub.f of the pulses of the picture and luminance signals shown in FIG. 11 become even longer.
Next, the relationship of display statuses to the logics of the picture signal and luminance signal will be described with reference to FIG. 13.
FIG. 13 is a table which expresses the relations of the display statuses with the logics of the picture and luminance signals. As indicated in the figure, in a case where the logic of the picture signal is false, no display is presented, and the logic of the luminance signal is neglected. In a case where the logic of the picture signal is true, the luminance signal becomes significant, and it is logically required that the luminance of the display change depending upon the logic of the luminance signal.
As described above, with the prior-art display control apparatus, it is logically required that no display be presented in the case where the picture signal is false and where the luminance signal is true. Due to rise and fall times of the signals, both picture and luminance signals, being above a threshold value, are considered true during time intervals Tl.sub.1 and Tl.sub.2, as shown in FIG. 14. than the response time of the display equipment, there is the disadvantage that, unlike the no-display status, high luminance displays are presented as abnormal displays during the time intervals.